Controller-decoder system requirements derived by implementing Shor's algorithm with surface code

Yaniv Kurman; Lior Ella; Nir Halay; Oded Wertheim; Yonatan Cohen

doi:10.22331/q-2026-07-22-2170

Controller-decoder system requirements derived by implementing Shor’s algorithm with surface code

Yaniv Kurman, Lior Ella, Nir Halay, Oded Wertheim, and Yonatan Cohen

Quantum Machines Inc., Tel Aviv, Israel

Published:	2026-07-22, volume 10, page 2170
Editor:	Philipp Schindler
Eprint:	arXiv:2412.00289v4
Doi:	https://doi.org/10.22331/q-2026-07-22-2170
Citation:	Quantum 10, 2170 (2026).

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Abstract

Quantum Error Correction (QEC) is regarded as the most promising path to quantum advantage. The success of QEC relies on achieving quantum gate fidelities below the error threshold of the QEC code, while accurately decoding errors through classical processing of the QEC stabilizer measurements. In this paper, we uncover the critical system-level requirements from a controller-decoder system (CDS) necessary to successfully execute the next milestone in QEC: a non-Clifford circuit. Using a representative non-Clifford circuit, of Shor factorization algorithm for the number 21, we convert the logical-level circuit to a QEC surface code circuit and finally to the physical level circuit. By taking into account realistic implementation aspects using typical superconducting qubit processor parameters, we reveal a broad range of core requirements from any CDS aimed at performing error corrected quantum computation. Our findings indicate that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable by distributing decoding data into several decoders while ensuring fast communication between decoders and with the controller. By extending existing simulation techniques, we simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance in the scale of 0.1% physical error rates and 1000 qubits, are sufficient for a successful circuit execution. Overall, the requirements outlined here set the stage for near- and medium-term experimental realizations of non-Clifford QEC circuits.

Featured image: The controller-decoder system for a non-Clifford surface-code circuit: (a) logical circuit factoring 21, (b) surface-code patch, (c) control stack linking the quantum processor, controller, and decoder in real time.

A video of the physical-level gate sequences for the factorization circuit with distance-3 surfaces. (doi.org/10.5281/zenodo.17970554)

Popular summary

Here we derive the controller-decoder system requirements for running non-Clifford circuits with quantum error correction — the next milestone for QEC experiments. Using a 5-qubit circuit that factors the number 21 with Shor's algorithm, we break the logical circuit down step by step into its error-corrected and physical-level implementations, extracting concrete numbers: microsecond-scale controller-decoder communication, the required decoder architecture, and real-time control operations.

► BibTeX data

@article{Kurman2026controllerdecoder,
  doi = {10.22331/q-2026-07-22-2170},
  url = {https://doi.org/10.22331/q-2026-07-22-2170},
  title = {Controller-decoder system requirements derived by implementing {S}hor's algorithm with surface code},
  author = {Kurman, Yaniv and Ella, Lior and Halay, Nir and Wertheim, Oded and Cohen, Yonatan},
  journal = {{Quantum}},
  issn = {2521-327X},
  publisher = {{Verein zur F{\"{o}}rderung des Open Access Publizierens in den Quantenwissenschaften}},
  volume = {10},
  pages = {2170},
  month = jul,
  year = {2026}
}

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