Learning to rank quantum circuits for hardware-optimized performance enhancement
Q-CTRL, Sydney, NSW Australia, and Los Angeles, CA USA
| Published: | 2024-11-27, volume 8, page 1542 |
| Eprint: | arXiv:2404.06535v2 |
| Doi: | https://doi.org/10.22331/q-2024-11-27-1542 |
| Citation: | Quantum 8, 1542 (2024). |
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Abstract
We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit $ibmq\_guadalupe$ device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a $1.8\times$ reduction in selection error when compared to the baseline approach and a $3.2\times$ reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.
Featured image: Machine learning pipeline for layout selection. (a) Layout generation. Graphs indicate connectivity of $\textit{ibmq_guadalupe}$ device: graph nodes indicate qubits and colored nodes are guides to the eye indicating different layouts for a notional five-qubit circuit. Only three layouts, A-C, shown for visual clarity. Different layers represent sets of layouts for different initial circuits. Purple QPU icons indicate hardware execution. The black database icon indicates that data from hardware execution form a dataset. (b) Overview of training phase. Ordering of layouts is now set by ranking conducted using current state of model. Purple dashed arrows indicate mismatches between model prediction and true ranking determined by database. The lower arrow indicates an iterative loop to minimize loss function via model parameter updates. (c) Overview of inference phase. The highest-ranking layout is selected for hardware execution, indicated by purple shading. There is no restriction that these layouts be present in the dataset, and in the primary use-case, the goal will be to predict layout rankings when the true ranking is unavailable.
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