Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes

Julien du Crest1, Francisco Garcia-Herrero2, Mehdi Mhalla3, Valentin Savin4, and Javier Valls5

1Université Grenoble Alpes, Grenoble INP, LIG, F-38000 Grenoble, France
2Department of Computer Architecture and Automatics, Complutense University of Madrid, Madrid, Spain
3Université Grenoble Alpes, CNRS, Grenoble INP, LIG, F-38000 Grenoble, France
4Université Grenoble Alpes, CEA-Léti, F-38054 Grenoble, France
5Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universitat Politecnica de Valencia, Valencia, Spain

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The inherent degeneracy of quantum low-density parity-check codes poses a challenge to their decoding, as it significantly degrades the error-correction performance of classical message-passing decoders. To improve their performance, a post-processing algorithm is usually employed. To narrow the gap between algorithmic solutions and hardware limitations, we introduce a new post-processing algorithm with a hardware-friendly orientation, providing error correction performance competitive to the state-of-the-art techniques. The proposed post-processing, referred to as check-agnosia, is inspired by stabilizer-inactivation, while considerably reducing the required hardware resources, and providing enough flexibility to allow different message-passing schedules and hardware architectures. We carry out a detailed analysis for a set of Pareto architectures with different tradeoffs between latency and power consumption, derived from the results of implemented designs on an FPGA board. We show that latency values close to one microsecond can be obtained on the FPGA board, and provide evidence that much lower latency values can be obtained for ASIC implementations. In the process, we also demonstrate the practical implications of the recently introduced t-covering layers and random-order layered scheduling.

In this work, we describe and analyse a new post-processing for message passing decoding of Quantum LDPC codes that can be run efficiently on parallel architectures.

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