Democratizing Spin Qubits

I've been building Powerpoint-based quantum computers with electron spins in silicon for 20 years. Unfortunately, real-life-based quantum dot quantum computers are harder to implement. Materials, fabrication, and control challenges still impede progress. The way to accelerate discovery is to make and measure more qubits. Here I discuss separating the qubit realization and testing circuitry from the materials science and on-chip fabrication that will ultimately be necessary. This approach should allow us, in the shorter term, to characterize wafers non-invasively for their qubit-relevant properties, to make small qubit systems on various different materials with little extra cost, and even to test spin-qubit to superconducting cavity entanglement protocols where the best possible cavity quality is preserved. Such a testbed can advance the materials science of semiconductor quantum information devices and enable small quantum computers. This article may also be useful as a light and light-hearted introduction to quantum dot spin qubits.


Introduction
The two states of a qubit are realized in the spin of an electron, spin up and spin down. A single electron can be trapped in a semiconductor box, called a quantum dot ( Figure 1). In silicon-currently the most promising material for spin-based quantum computing-the indirect band-gap means that the electron has extra nearby energy levels due to different combinations of the conduction band minima or "valleys" where the electron exists. Temperature, noise, and gate operations can cause unwanted excitation into these states. This so-called "valley splitting" problem, especially in silicon-germanium quantum dots, impacts yield, initialization/readout, and quantum operations, and originally motivated this work. Although obscure, this materials science issue is a roadblock to quantum information processors in silicon, and valley splitting is only representative of a greater challenge.
Like for other qubit parameters such as coherence time and operation error rates, to measure the valley splitting one must fabricate a quantum dot and test it, typically at dilution refrigerator temperatures 1 . The general difficulty in making qubits in semiconductors has hampered progress in the field. Exciting recent successes-functional dot qubits and compelling quantum gate demonstrations [1][2][3][4][5][6][7][8][9][10][11][12]-have taught us a lot about how to make good qubits. Yet there is a high barrier to entry for new experimental groups compared to, say, superconducting qubits.  Figure 8: Results from 1D tight-binding model for wave functions for ground and excited valley states and valley splitting for a 10 nm quantum well. The z-component of the electron dot wave function is the output of a 2-band tight-binding calculation (points) which has been interpolated (line) for a typical SiGe heterostructure with a quantum well of 10 nm, barriers of 150 meV, and a large growth direction electric field due to space-charge separation from the donor layer of 6 ⇥ 10 6 V/m. Valley splitting in realistic silicon quantum dots will likely be reduced versus the 1D results presented here due to interface roughness/steps, etc.
where v is the valley splitting, z0 is the extent of the wave function (assumed gaussian) inẑ and qu is the phonon wave length of the emitted Umklapp phonon, qu = 0.3kmax. The details of this calculation are given in Appendix IX B. Let us compare Eq. 16 to pure orbital relaxation, Eq. 10. At first glance, the valley relaxation rate has a 3 dependence as opposed to a 4 in the orbital case (assuming parabolic dot potentials for both and matrix elements given due to gaussian wave functions). To understand this remember that for valley relaxation this transition occurs within the lowest manifold (both initial and final states have the same s-like envelope function) such that the matrix elements M ⇠ 1. In the orbital case, we must calculate matrix elements from 2p-like to 1s-like states, such that M _ x 2 0 _ . The valley relaxation expression also includes prominently a exp( z 2 0 q 2 u /4) prefactor absent in the exact orbital case (Eq. 10). This prefactor predicts that the phonon relaxation rate will be peaked at the Umklapp phonon energy (assuming z0 is constant with v , which it isn't). Equation 16 also shows the importance of the z0 extent of the wave function; decreasing z0 increases the relaxation rate. These effects are related, in that Umklapp phonons at qu = v /~vl,t which connect valleys in neighboring Brillouin zones are the most efficient relaxation channel (see Appendix IX B for more details). Figure 7 explicitly shows the valley relaxation rate in the two cases of fixed z0 wave function height and wave function height that changes accurately with electric field and valley splitting. It turns out that the Bloch coefficients to the nearest valley at 0.3kmax are most efficient and phonons are then emitted in the Figure 1: Spin qubit in silicon. a) A trapping potential due to a heterostructure box or donor atom hosts our electron. For SiGe barriers above and below a strained-Si quantum well, the trapping potential is roughly 50 meV per 10% Ge in the barriers. b) The energy levels can be labeled like an atom if we assume an effective mass theory [13] (note that the real wave function of the electron also has Kohn-Luttinger oscillations [14,15] due to the conduction band valleys at~0.8k max and atomistic oscillations from the crystal underneath this envelope). The "valley-splitting" between the states can range from 0 to several meV. c) The conduction and valence band symmetry governs possible additional levels. For electrons in strained-silicon quantum wells or at inversion layers, there are two occupied conduction band minima and thus double the number of states (the other four states are pushed much higher in energy due to the strain or confinement, respectfully).
Do superconducting qubit experimentalists have it easy? Yeah, they kind of do. The robust 2 transmon qubit [16][17][18] requires only one layer of metal, with large lithographic dimensions [19]. The transmon and variants can be characterized and controlled with a single microwave cavity/generator/line or even wirelessly via a properly designed superconducting cavity ( Figure 2). Superconducting circuits can be floating, requiring no source or sink of carriers. In contrast, consider what we know now as best practices for making a lateral silicon quantum dot qubit ( Figure 3). One needs to make very small dots (due to the relatively large effective mass of silicon), with multiple layers of overlapping or tightly-aligned metal gates to limit cross-capacitance between dot gates 3 , all with O(10 nm) wire-widths at 50-100 nm wire pitch. Poor yield to disorder is a major problem. Worse, the materials stack is critically important to whether the dot qubits work at all or have desirable qubit properties. Spin-based quantum dot qubits also need multiple physical wires per dot and often nearby charge sensors (for spin-to-charge conversion-based readout [20]). This level of complexity in fabrication-which must be coupled with good materials science properties of the wafer and the gate stack-retards both new qubit exploration and characterizing many, individual quantum dots to optimize materials parameters.
We can separate the materials science challenge from the "making the dots and measure them" challenge. If the dots and associated readout circuitry can be made on another circuit chip or board, then the actual qubit-hosting wafer can be optimized separately. (And even made of different crystals such as germanium). The idea of "flip-chip" engineering has already been applied successsfully in the superconducting context [21,22], while the concept of a "probe" trap has been used in ion trap quantum computing [23,24] to search for heating mechanisms on relevant surfaces. In semiconductors, Ref. [25] and later Ref.  The transmon superconducting qubit is a single layer of metal and a shadow-evaporated junction. It is extremely robust in that nearly all fabricated qubits work. In a co-planar geometry a superconducting cavity can be used to readout the qubit (circuit QED). (b) A crucial step to advance the field was applying these same ideas to a 3D geometry. By going larger the participation of loss mechanisms was proportionally lowered and allowed systematic study of qubits with longer life while the more scalable 2D qubits were catching up in performance. But perhaps more interesting, the wireless approach can allow different types of qubits to be tested more quickly, even as in (c) fluxonium, where there isn't a natural coupling to an electric field (an antenna can be used to couple to the 3D field). (Figures 2b and 2c courtesy Yale.) a testbed where dots are induced and measured by a separate chip to characterize materials [27] and qubit approaches. In doing so, an acceleration of progress similar to that driven by the "wireless" 3D transmon ( Figure 2b) could be replicated in the spin community.
There are other ways to democratize spin qubits. One can distribute known good devices to academic groups interested in exploring new qubit encodings and ways to control them; this is the foundry model 4 . Increasing throughput of testing at multiple temperature stages (room temperature, 1 to 4K depending on the physics, and <100 mK) also directly benefits fabricated device optimization. Recent work toward a cryo-prober [28], particularly at 1-2K where dot physics starts to correlate with qubit performance, will accelerate yield of critical parameters. However, dilution refrigerators (DR) are needed for the most advanced qubit measurements (relevant to target applications). Cryogenic switches inside the DR will allow for a handful of quantum dot systems to be measured in sequence without a fridge warm-up.

Making a quantum dot qubit without fabricating a quantum dot
A spin qubit is formed from the Zeeman split sub-levels (see Figure 1b) of the ground state of an electron trapped in some potential inside a semiconductor. That electrostatic potential can be artificial, formed from the combination of a heterostructure 5 and an external voltage [31], or natural, the pull of an implanted donor [32]. The lowest levels of SiO2 +V n mode designs use rger than the spatial tions. 9 As a result, it ctronic confinement number of quantum nement potential on designs, 10,11 where sitively biased gates um" gate designs 12 ) l on a much smaller nt. urable accumulation ree overlapping aluure has two parallel One of the channels tum dots, while the rge sensor quantum gate architecture is wing a higher degree evices. 12 Direct local ss-coupling, simpliots and tuning of the monstrated here prong to a larger series ired number of gate rly as 2N þ 1. ped Si/SiGe heteroin Fig. 1(a). A SiGe Si wafer by linearly 30% over 3 lm. The olished before grow-3 layer, followed by m Si 0.7 Ge 0.3 spacer, is uniaxially strained ricated on this wafer yield a two-dimensional electron gas (2DEG) carrier mobility l ¼ 1:6 Â 10 5 cm 2 /Vs at an electron density n ¼ 2:2 Â 10 11 /cm 2 and temperature T ¼ 350 mK. A valley splitting D v ¼ 150 leV is measured at a magnetic field B ¼ 1.8 T. The 2DEG also undergoes a metal-to-insulator transition (MIT) at a critical density n c ¼ 0:46 Â 10 11 /cm 2 . beam epitaxy ͑see Fig. 2͒. By doping the AlGaAs layer with Si, free electrons are introduced. These accumulate at the GaAs/ AlGaAs interface, typically 50-100 nm below the surface, forming a two-dimensional electron gas ͑2DEG͒-a thin ͑ϳ10 nm͒ sheet of electrons that can only move along the interface. The 2DEG can have high mobility and relatively low electron density ͓typically 10 5 − 10 7 cm 2 / V s and ϳ͑1 − 5͒ ϫ 10 15 m −2 , respectively͔. The low electron-density results in a large Fermi wavelength ͑ϳ40 nm͒ and a large screening length, which allows us to locally deplete the 2DEG with an electric field. This electric field is created by applying negative voltages to metal gate electrodes on top of the heterostructure ͓see Fig. 2͑a͔͒.
Electron-beam lithography enables fabrication of gate structures with dimensions down to a few tens of nanometers ͑Fig. 2͒, yielding local control over the depletion of the 2DEG with roughly the same spatial resolution. Small islands of electrons can be isolated from the rest of the 2DEG by choosing a suitable design of the gate structure, thus creating quantum dots. Finally, low-FIG. 2. Lateral quantum dot device defined by metal surface electrodes. ͑a͒ Schematic view. Negative voltages applied to metal gate electrodes ͑dark gray͒ lead to depleted regions ͑white͒ in the 2DEG ͑light gray͒. Ohmic contacts ͑light gray columns͒ enable bonding wires ͑not shown͒ to make electrical contact to the 2DEG reservoirs. ͑b͒, ͑c͒ Scanning electron micrographs of ͑b͒ a few-electron single-dot device and ͑c͒ a double dot device, showing the gate electrodes ͑light gray͒ on top of the surface ͑dark gray͒. White dots indicate the location of the quantum dots. Ohmic contacts are shown in the corners. White arrows outline the path of current I DOT from one reservoir through the dot͑s͒ to the other reservoir. For the device in ͑c͒, the two gates on the side can be used to create two quantum point contacts, which can serve as electrometers by passing a current I QPC . Note that this device can also be used to define a single dot. Image in ͑b͒ courtesy of A. Sachrajda.

I. RESULTS
Device architecture. Figure 1 shows a scanning electron micrograph (SEM) and cross-sectional schematic of the device, which incorporates 7 independently controlled aluminium gates. When a positive bias is applied to the lead gates (L1 and L2) an accumulation layer of electrons is induced under the thin SiO2, to form the source and drain reservoirs for the double dot system. A positive voltage on the plunger gate P1 (P2) causes electrons to accumulate in Dot 1 (Dot 2). Independent biasing of P1 and P2 provides direct control of the double-dot electron occupancy (m, n). The tunnel barriers between the two dots and the reservoirs are controlled using the barrier gates: B1, B2 and B3. The middle barrier gate B2 determines the inter-dot tunnel coupling. The electrochemical potentials of the coupled dots can also be easily tuned to be in resonance with those of the source and drain reservoirs. As shown in Fig. 1(b), gates L1 and L2 extend over the source and drain n + contacts, and also overlap gates B1 and B3. The upper-layer gates (P1 and P2) are patterned on top of the lead and barrier gates. The lithographic size of the dots is defined by the distance between adjacent barrier gates (⇠30 nm) and the width of the plunger gates (⇠50 nm), as shown in Fig. 1(a).
Inter-dot tunnel coupling tunability. Figure 2 shows the measured di↵erential conductance of the device as a function of the plunger gate voltages, VP1 and Characteristics at di↵erent inter-dot tunnel coupling. Measured stability diagrams and energy landscape of the double dot system ranging from weak to strong interdot tunnel coupling (a) (c) and (d) (f) respectively, for VL1 = VL2 = 3.0 V, VB1 = 0.76 V, VB3 = 1.0 V and VSD = 0. From lower to higher VB2, the tunnel barrier height decreases resulting in stronger inter-dot tunnel coupling. (a) A checker box pattern, (b) honeycomb pattern and (c) diagonal parallel lines indicate that the two dots merge into a single dot as the coupling is increased [23].
VP2, with all other gate voltages held constant, together with sketches of the energy landscape of the double dot. The charge-stability maps moving from Fig. 2(a) to 2(c) clearly show the e↵ects of an increasing inter-dot coupling as the middle barrier-gate voltage VB2 is increased, lowering the tunnel barrier between the dots. Fig. 2(b) shows the characteristic honeycomb-shaped stability map representing intermediate inter-dot coupling [23], obtained at VB2 = 1.32 V. At lower middle barrier-gate voltage, VB2 = 1.20 V, we observe a checker-box shaped map [ Fig. 2(a)], since the middle barrier is opaque enough to almost completely decouple the two dots. In contrast, the stability map in Fig. 2(c) shows the formation of diagonal parallel lines at VB2 = 1.40 V. Here the two dots e↵ectively merge into a single dot due to the lowering of the middle barrier [ Fig. 2(f)]. The transport measurements shown here do not allow a precise determination of the electron occupancy (m, n) in the dots, since it is possible that electrons remain in the dots even when ISD is immeasurably small. For the regime plotted in Fig. 2 there were at least 10 electrons in each dot, based on our measurement of Coulomb peaks as we further depleted the system. An absolute measurement of dot occupancy would require integration of a charge sensor into the system [7]. These results nevertheless demonstrate that the multi-gated structure provides excellent tunability of coupling while maintaining charge stability over a wide range of electron occupancy.
Capacitances and charging energies.  Figure 3: Quantum dot, simplified. a) Early depletion mode quantum dots (modeled on GaAs quantum experiments before them) utilized doping layers (modulation doping) and negatively charged metal top gates to push away all electrons but one [29]; these suffered from severe disorder when implemented in silicon. b) Accumulation mode devices use overlapping gates to form dot and tunnel gates and represent the current state of the art [2,3,30]; often a nearby charge sensor (also a dot) is used for spin-charge readout. Here, the doping layer can be removed if implanted electron sources (donor-implanted regions in the crystal) are nearby. c) A single quantum dot potential in it's simplest form. d) A quantum dot created with a single gate wire whose electrostatic potential has already trapped an electron in the quantum well. (Top row device images are courtesy TUDelft, Princeton, and UNSW.) one or more electrons or holes inside a single dot can form a qubit. Alternatively, a qubit can be "encoded" 6 into the larger Hilbert space of multiple separate quantum dots (e.g., [33][34][35][36][37][38][39]). Each approach has different, potentially useful properties for quantum computing. Typically, 1 or 3 electrons are loaded per dot 7 in a roughly parabolic potential in the plane of the two-dimensional electron gas (2DEG) or inversion layer. The potential must be deep enough such that the excited state orbital levels ("p-like" envelope functions 8 ) are well above the energy of thermal excitations (∼ kT ). In an indirect band-gap semiconductor like silicon, the electron wave function is a superposition of all the conduction band minima (or valleys). This valley degeneracy is lifted by strain or an abrupt potential.
(Alternatively, holes exist at the top of the valence band at the Γ-point and can be considered spin-3/2 particles, although there are sometimes nearby heavy-hole or SOC split bands.) Somewhat surprisingly, the spin splitting (linearly proportional to the magnetic field) can be smaller than the effective temperature and typically is in many experiments [1]. Kramers degeneracy (where a "forbidden" very tiny matrix element connects phonons between the two spin states) results in extremely long lifetimes for spins in some solids, a fact that has been known at least since the 1950s [40,41]. (The same can also be true for some hole states, e.g. [42].) When designing a quantum computer based on quantum dots, we care about a number of intrinsic parameters derived from the quantum dot potential, material and material stack, the proximity of other qubits/defects/oxides/gates, and other parameters that are relevant for two qubit operations. These parameters include the level structure of the dot (or spectroscopy of the excited states), the spontaneous decay time (called the T 1 time, almost always due to emission of a phonon at these dilution refrigerator temperatures, but more complicated above~1K), and the decay of the coherence of the qubit as a function of time (or T * 2 for the specific 1/e time assuming an exponential fall-off, which is actually not usually the case). All these parameters can change with the number of particles per dot and if multiple dots are coupled together, either via the Pauli exchange interaction or capacitively.
Let us consider the simplest quantum dot, using best practices from recent progress (Figure 3). Our options include semiconductors such as GaAs, silicon, germanium. GaAs has spinful nuclei, leading to poor T * 2 times (~ns). Germanium is interesting as discussed below. But the pull of silicon is strong due to the CMOS industry (ultra-chemically pure and perfect crystals, precision lithography, good dielectrics) and the fact that isotopically enriched silicon exists and is available (where the spin-1/2 Si 29 nuclei have been removed leaving only spin-0 silicon-28), leading to extremely long coherence times [43].
First, create an electrostatic trap for the electron in the growth direction, z, by making either a "quantum well" or an inversion layer. For the former, use a strain-engineered SiGe-Si-SiGe sandwich [44]. For the latter, use the well-known oxide-silicon (MOS) interface of  Figure 1a). There are no electrons until we put them there (assuming no doping). Due to the effective mass of electrons in silicon, to get an orbital splitting of~1meV = 10K, we need an effective "box" of~30 nm laterally. Finally, a combination of negative (depletion) and positive (accumulation) gates can form the trap in the (x, y) plane creating our dot potential. Because of the large effective mass of electrons in silicon compared to GaAs 9 , the community has learned that unwanted "dots" (think a disordered eggshell container) can form in the quantum well via the presence of donors, or by possibly tiny strain due to metallic gates [45] on the surface. Therefore, don't dope the quantum well. Instead, implant donors in source regions creating a bath of electrons that can be brought electrostatically near the active quantum dots with gates. And make the gates as uniform ("total coverage") and as far away as possible. This is how the best arrays of lateral quantum dots for qubits are fabricated today (Figure 3).
To induce a dot potential, only a single wire is needed (Figure 3d). This can be formed from a metal gate on the dot wafer surface, or, by a wire on a different chip or probe tip (with a positive voltage, appropriate geometry, and distance from the target active layer [27]). Indeed, Scanning Tunneling Microscope (STM) tips have been used in the past to induce dots on the surface of materials [46,47]. Thus, the simplest dot doesn't require fabricating a dot on the "dot chip" at all. Instead, fabricate a "dot inducing chip" or gate chip on a separate substrate, with a single layer of metal. Then place that perpendicular to the "wafer chip" (touching or not) to where the dot is actually intended to be created. All the circuitry we need to measure the dot can be off the wafer chip under test.
Consider three (increasingly demanding) options for loading electrons into the induced quantum dot (Figure 4). Option 1: shine light with energy above the band-gap on the wafer to generate carriers 10 , Figure 4a. Generate enough carriers and our dot will trap one (or more, depending on the depth of it's trapping potential). Option 2 (perhaps only suitable to STM-like, single tip, set-ups): Figure 4b, move the inducing gate to an implanted region on the wafer and physically move the loaded dot away from it to isolate the dot. Option three: add other lead(s) to the gate-chip, including a much wider and fatter "bath" gate ( Figure 4c) that can bring electrons into the channel from the implanted region to the dot much like is already done. Implanting is a standard procedure and requires a mask but can be outsourced. (So we've broken the non-invasive pledge for options two and three.) a c b

Characterizing an induced quantum dot
An electron must be present in the induced quantum dot to have a qubit. If the dot is truly isolated with only one wire to both maintain the potential and probe the dot, that is really hard to do. Best practice for qubit measurement is to create a nearby quantum dot charge sensor (see the top-down SEM image in Figure 3b for an example). 11 By pulsing the electrons in the dots one can figure out how to convert the spin information to different charge distributions, detectable with the readout dot. However, since we only have a single wire, a better option is to use so-called (in the dot community) dispersive readout. A tank circuit is attached to a nearby dot gate. Small changes in the quantum capacitance as seen by that gate (or more generally the curvature coupling [48]) are detected by measuring the phase shift of a reflected rf-pulse (dispersive shift of the resonator) at the resonator frequency (where the frequency is relatively low, 100 Mhz to 500 MHz) [49][50][51][52][53][54][55][56]. Note that this technique as applied so far has only worked in two ways: detecting a signal when electrons tunnel in and out of a nearby bath (so-called "tunneling" capacitance) or at a  charge transition (e.g. between dot occupations 1, 1 to 2, 0, see Figure 8 for a preview) to a nearby dot. 12 These signals map out 0, 1, etc. electrons in the dot. A higher-frequency resonator can also be used as in [57,58], putting the cavity into the quantum regime (and increasing compatibility with superconducting amplifiers). Ref [27] showed that it may be possible to measure the small energy band curvature ( Figure  5a) due to a single, stationary electron as compared to no signal (no electron trapped). Assuming the use of a superconducting resonator in series with the dot-inducing gate, quantum capacitances as low as 0.01 attoFarad should be observable if a Q ∼ 10 5 can be achieved (see [27] for details), allowing for the detection of electrons with a single lead without tunneling transitions to a reservoir or dot (which has never been seen before). If the measurement apparatus is fast enough then the appearance of an electron from the bulk (due to light-created carriers for example) may be observable. If these don't work, then using the bath gate or a nearby dot (a 2 dot probe) will be necessary, more complicated, but making all the known techniques for qubit characterization available.
With the electron number in the dot known, let's focus on spectroscopy, or charting of the excited states of the dot. Doing so solves our original problem of measuring the valley state across a chip non-invasively. Ref [27] proposes solutions for a single wire. At the magnetic field that equals the valley splitting energy, there is an anti-crossing which results in a quantum capacitance change. With two electrons in the dot, the curvature is even larger and occurs in the ground state (Figure 5b). Detecting this curvature allows the valley splitting to be measured by sweeping the magnetic field (or valley splitting via E z over a smaller range). Doing precise spectroscopy requires a relative energy scale. The magnetic field provides that if it can be well calibrated. Another option is to introduce another rf field which drives transitions in the dot. Unfortunately, given the large possible range of valley splittings, and the possibility of very large orbital splittings (up to 8 meV), tunability of the microwave field would have to be over a vast range for a single dot. With two dots a new energy scale emerges, the detuning between the two dots, and there are many more options; valley spectroscopy can be achieved without a magnetic field [59]. The reflectometry approach allows one to measure the critical parameters of the system even if the excited states are much larger than the cavity frequency and for arbitrarily high valley splittings in a two dot system.
To summarize, with a single wire we can detect if there is an electron in the dot and measure the valley splitting given some rather stringent requirements. There are other ways to measure valley splitting: already demonstrated techniques like photon-assisted tunneling, that involve multiple dots or tunneling to leads. Those can also be realized in multi-lead systems.

Characterizing an induced quantum dot quantum computer
Imagine a one-dimensional array of dots induced by a gate-chip on a chip wafer. Illustrations of such systems are shown in Figures 6 and 7. It is possible to make two dots with just two wires, and for many years the community relied on detuning of energy levels between dots to produce two-electron interactions. Now it is understood that using a barrier gate to control electron wave function overlap is better. 13 Using the barrier gate allows for operation at a sweet spot (symmetric operating point) [5,6] and it is less sensitive to charge noise than the plunger gates above the dots [60] (the exchange interaction is less sensitive to the tunnel barrier than to the detuning, so charge noise is minimized by using only high speed lines on the barrier if possible). Moving to multiple wires allows one to measure dot qubit quantum properties such as coherence times and even do quantum operations, that is, make a small quantum computer.
Let's quickly go through a sequence of experiments that would characterize the wafer in question (Figure 8). With a multi-wire device it is natural and preferable to use a bath gate to load electrons. In this context our first experiment is to chart out the charge stability diagram for loading electrons from zero. To do this we vary V P 1 versus V T 1 , where V P 1 is the dot gate and V T 1 is a tunnel gate between the bath and the dot. One should see lines in this plot indicating the transitions between n − 1 and n electrons (Figure 8a). (The straighter the line the better, it indicates small cross capacitance of the gates. Curviness means changing cross capacitance which is very bad because the electron is moving. It also makes it harder to dynamically compensate for such gates [61,62].) Once we can reliably load single electrons, then charge stability diagrams (P vs. P, see Figure 8b) would be performed to map out the parameter space of the two dot system. An increasingly useful metric once this stage is reached is the charge-noise spectrum of each dot (e.g., [63]), which can be extracted via resonator measurements [64].
To do quantum coherent measurements we need to actually measure the spin qubits. Incorporating readout allows one to experimentally determine the coherence time (T 2 ) and lifetime (T 1 ) of the qubits as well as the error rates of one and two-qubit operations with the right pulse sequence. Combining quantum capacitive readout 14 with Pauli-blockade gives a proven means of differentiating the singlet versus triplet states of the two dots 15 .  [5,6]. The lower plot shows a so-called "fingerprint" plot demonstrating the dependence of exchange on ∆ and V T 2 . In this plot the average singlet probability is shown after evolving for 500 ns at a potential specified by the axes [5] (both c plots courtesy HRL).
If you detune the dots into the Pauli-blockade regime (where the (1,1) state equals the (0,2) state of the double dot system), one can distinguish singlet from triplet: the singlet state will tend to allow two electrons to go into the lower dot, when combined the dots are in the triplet state, they will each stay in their respective dots as the transition won't be allowed [20]. This is sensitive to a readout window given by the temperature and the singlet-triplet relaxation time, but the signal can still be strong [65].
Another option for qubit readout, as advocated by us recently [48], is to attempt quantum curvature readout deep in the (1,1) regime, where the curvature of the singlet and triplet states is detected within the S-T relaxation time [38,48]. This approach has the benefit of being quantum non-demolition (the qubit is preserved) and the symmetry of the dot decreases sensitivity to charge noise and increases S-T relaxation time (because the transition dipole matrix elements between S and T vanish). It should also be noted (although this is the first place we have noted it), that this approach has some immunity to temperature -so may be the most compatible readout approach for high temperature qubits in relatively small magnetic fields.
Exchange is the fundamental interaction between electrons related to the Pauli exclusion principle that allows for fast two-qubit gates with large ON/OFF ratios. As changing the gate potentials results in the electron wave functions in the two dots overlapping, the spin state of the combined system evolves. If this interaction is timed just right a given two-qubit spin operation can be achieved resulting in an entangling gate between the qubits [31]. Quantum operations can be analyzed by measuring Rabi oscillations when the tunnel conversion to a singlets or triplets of two dots.
barrier is lowered to turn on the exchange interaction. The latter, if done at the symmetric operating point, allows one to characterize the charge noise of the device as once you turn on exchange, the spins are no longer "protected" to noise on their wave functions. More oscillations are indicitave of less charge noise. A useful variant of this latter experience is to perform a fingerprint plot (see Figure 8c).

Caveat Emptor
The cartoons drawn here are just that. Realization will be more difficult than imagined and different than proposed. But ideally, the separation of material optimization from qubit formation will help push the limits of possible fidelity, or yield, or valley splitting, or whatever is limited by the material properties. Even when realized and assuming success, there will still be concerns in translating knowledge gained from the gate-chip induced dots as compared to the "real thing." Assuming the wafer has been optimized fully, there could be drastically different results when the dots are fabricated in a more scalable manner.
Materials science still matters. Fabricating the gates with the associated interfaces, dielectrics, processing steps (e.g., anneals) will affect critical parameters like valley splitting and charge noise. Complex surface physics due to the passivation of the silicon/silicongermanium surface can create unwanted potentials on the quantum dot plane in the quantum well case or a charge noise environment different than or worse than a full gate stack. Our hope is that the surface can be treated in such a way to minimize negative impact.
Shaking of the gate-chip will result in moving of the electrons (with some symmetry) if the gate-chip is not mounted statically to the dot wafer. We have not seriously considered the possible implications of this vibration on dot and quantum operation parameters. Although any length scales of movement are likely much larger than the dots, and a much lower relevant frequency compared to gate speed (nanoseconds). There can also be a vacuum penalty: if the wire is too far from the surface than the potential of the dot can be washed out. Our point design simulations indicate that 10 nm separation still allows for sufficient dot confinement (while STM tunneling typically occurs~1 nm from the surface distances,~10 nm can be gauged with a field emission current). Static mounting, intimate connection (via a 2D flip-chip instead of perpendicular), and fast readout can mitigate these concerns.
The approach still requires dilution fridge temperatures unless the qubits can operate and be operated on at higher temperature (more below). Qubit operations (e.g., an encoded CNOT gate made up of 20+ pulses) are just as difficult control-wise. Metal shields (that is, a multi-layer gate chip) above and below the dot gates may be needed to decrease cross capacitance or improve screening.
A linear array of qubits limits scalability. Introducing longer distance couplers can connect arrays in a 1.5 dimensional geometry (still linear but with long-distance coupling via resonators and select dots). To keep things simple we have discussed one layer of metal on the gate chip but the concept can get more complicated (wafer to wafer integration instead of perpendicular chips; multiple layers on the gate chip, etc).

What would I do?
Physics.
1) Let's characterize quantum-relevant wafer properties, especially valley splitting, charge noise, and disorder, across enough wafers and "devices" to be statistically conclusive.
2) Investigate proposed qubit approaches, encodings, and operation protocols on one, two, three, and four dot systems [31, 34, 36-39, 66, 67]. There are too many unexplored proposals to enumerate, but we still don't understand in practice which qubit encodings offer the best trade-offs for qubit quality and classical overhead (number of dots, pulses, etc), including protocols to minimize leakage [36,68,69] and explore measurementbased schemes [70]. In particular, proposals for encoded qubit interconversion and noiseinsensitive always-on, exchange-only qubits [38] could be validated or dismissed. A ten dot device would be sufficient to implement the vast majority of qubit and gate proposals.
3) Explore alternative readout and coupling approaches via classical and quantum cavities: transverse versus longitudinal coupling versus modulated longitudinal coupling [48][49][50][51]71]. 4) Investigate different materials for their relevance to quantum computing: Optimizing valley splitting: various proposals have been made to increase valley splitting. Because all of them depend on the microscopic details of the heterostructure stack, many devices will need to be measured to have confidence in a solution. Holes: Holes exist at the Γpoint of the valence band, so there are no valley splitting issues (although there may be spin-orbit bands nearby). Germanium: germanium has a lower effective mass for holes (as compared to electrons in silicon) which would relax the gate wire pitch requirements (and sensitivity to disorder); using holes in Ge may offer larger spin-orbit coupling as well as no complicating valley splitting physics. Very recent progress in germanium quantum dots has been promising [72][73][74]. III-Vs: Although III-Vs suffer from spinful nuclei, they offer a benefit of a direct band gap (also plausibly realized in SiGe superlattices by the way). The gate-chip approach would allow continued cost-realistic research in III-Vs for optical conversion or for other materials, such as GaN. II-VIs: II-VIs offer the potential for quantum well dots with spin-0 nuclei and a direct band-gap, they are notoriously difficult to fabricate. ZnO and other oxide-based 2DEGs have shown inklings of relevance to quantum devices. 2D materials such as graphene and van der Walls heterostructures (layers of 2D materials) offer a very large phase space of possible dot implementations (with such materials, loss may be minimized), the approach here would greatly accelerate exploration of such materials. Super-Semi materials: In proximitized superconductingsemiconductor stacks, there are opportunities to explore different approaches to qubit formation via the split-chip approach presented here while minimizing loss in the substrate. Topological materials: Many potential topological materials are fragile to lithographic and gate processing. 5) Study high temperature qubits. Spin qubits continue to have long coherence times even at elevated temperatures relative to the Zeeman splitting [15,41,[75][76][77]. An open question is how robust a 2-qubit gate can be at elevated temperatures (350 mK or 1-4K). 6) Search for non-QC applications of these small quantum systems, such as an for current standards [78,79]. This approach may allow for far easier fabrication and potentially better charge noise characteristics.
7 One more thing: coupling spins to a superconducting cavity We've already discussed using superconducting resonators for readout, we can go further by exploring spin-qubit entangling protocols [71,80] via superconducting cavity or transmission lines. By putting the cavity on the gate-chip, see Figure 9, we can optimize for high Q. Certain entangling protocols may benefit from high-Q resonators. Resonators deposited on typical SiGe dot wafers, for example, tend to have Q's « 100,000 as compared to millions achieved on clean sapphire or silicon wafers. A similar approach can be made with  Figure 9: Superconducting cavity coupling of 2 encoded dot qubits. It's just as easy to put a superconducting metal on the gate-chip.
a flip-chip resonator and a traditional dot chip, but our approach should make fabrication much simpler. It should also allow networking of small qubit registers enabling a 1.5D quantum geometry.

End Speech
The introduction to virtually every silicon qubit paper goes something like this: silicon quantum dot spin qubits provide a promising platform for large-scale quantum computation because of their high-density, compatibility with conventional CMOS manufacturing, and long coherence times due to enriched 28 Si material and low spin-orbit coupling. The future of silicon quantum computing is strong, more-so given recent progress. Our difficulty has been that we must immediately go to the final dot dimensions just for the dots to work, we can't push it off. Qubits need to be small, materials need to be right, and microscopic effects matter immediately. Many of these problems will eventually need to be addressed in superconducting qubits, but now you can avoid them to make progress. It's become all the rage to be building "quantum testbeds". These testbeds put as many of the best qubits we have today together in order to run small algorithms, to achieve quantum supremacy! This will be exciting, and inconclusive, for some time. Going forward on this path is obviously necessary, and also toward the first true quantum error corrected logical qubit. Here I have in mind a different form of quantum testbed. My testbed can be used to improve or assess new materials stacks for qubits. It can be used to build few qubit system to test new designs. It is optimal for a materials-design-test cycle. Because it separates qubit design (gate structure) from wafer growth, both can be made better simultaneously. Shifting to a completely different type of material (e.g. holes in germanium versus electrons in silicon) requires at most a gate pitch change. There's also no reason one can't use this approach to make small quantum computers.
In summary, let us find a way to make and measure more semiconductor qubits, one way or another.