Dimensional Expressivity Analysis of Parametric Quantum Circuits
1Perimeter Institute for Theoretical Physics, 31 Caroline Street North, Waterloo, ON N2L 2Y5, Canada
2Computation-Based Science and Technology Research Center, The Cyprus Institute, 20 Kavafi Street, 2121 Nicosia, Cyprus
3Department of Mathematics, King’s College London, Strand, London WC2R 2LS, United Kingdom
4NIC, DESY Zeuthen, Platanenallee 6, 15738 Zeuthen, Germany
5Institut für Physik, Humboldt-Universität zu Berlin, Zum Großen Windkanal 6, D-12489 Berlin, Germany
| Published: | 2021-03-29, volume 5, page 422 |
| Eprint: | arXiv:2011.03532v3 |
| Doi: | https://doi.org/10.22331/q-2021-03-29-422 |
| Citation: | Quantum 5, 422 (2021). |
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Abstract
Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.
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